The invention concerns a sensing device for reading data stored in a passive matrix memory comprising memory cells in the form of ferroelectric capacitors, wherein said sensing device senses a current response corresponding to the data, typically a binary one or a binary zero, and performs an integration of two read values.
The invention also concerns a read method for use with the sensing device according to the invention, wherein the sensing device are used for reading data stored in a passive matrix memory with word and bit lines and comprising memory cells in the form of ferroelectric capacitors at crossings between the word and bit lines, wherein the sensing device senses a current response corresponding to the data stored in a memory cell, typically at binary one or a binary zero, and performs an integration of read values, wherein the read method comprises controlling the electric potentials on all word and bit lines in time latching word line potentials to potentials selected among predetermined word line potentials and either latching bit lines to potentials selected among predetermined bit line potentials, wherein bit lines in a read cycle are connected to the sensing device for sensing a charge flowing between a selected bit line and a memory cell at the crossing of the former and a word line activated by being latched to a selected potential for initializing the read cycle.
Ferroelectric matrix memories can be divided into two types, one type containing active elements linked to the memory cells, and one type without active elements. In the following focus is directed only towards passive matrix memories without active elements, such as diodes or transistors that are locally associated to the memory cells.
A ferroelectric matrix memory can have memory cells in the form of ferroelectric capacitors without active access elements such as an access transistor and comprises a thin ferroelectric material with a set of parallel conducting electrodes (xe2x80x9cword linesxe2x80x9d) deposited on one side and an essentially orthogonal set of conducting electrodes (xe2x80x9cbit linesxe2x80x9d) deposited on the other side. This configuration is referred to as a xe2x80x9cpassive matrix memoryxe2x80x9d. In the passive matrix memory, the individual memory cells are formed at the crossing-points of the opposing electrodes creating a memory matrix comprising memory cells that can be individually accessed electrically by selective excitation of the appropriate electrodes from the edge of the matrix.
To write to a memory cell, a positive or negative voltage is applied to the electrodes, causing the ferroelectric material to move along its hysteresis curve to a stable state corresponding to the written datum, a binary one or a binary zero. To determine the data thus stored in a ferroelectric capacitor, a voltage (typically in the form of a voltage pulse) is applied across the plates of the capacitor, whereby a current response is sensed by means of a sensing device, typically a sense amplifier. The sensing device is typically connected to a respective bit line, directly or via a multiplexer or gate.
One of the difficulties during sensing is to establish a reference being able to discriminate between a binary zero and a binary one. One solution is to introduce a reference voltage to the sense amplifier, which is described for instance in U.S. Pat. No. 5,905,671. Any observed signal above the reference is taken as one of two logic states, while any signal below the reference is taken as the other logic state.
However, there are several limits and drawbacks with the described reference method and similar direct reference methods, which will be further described below.
Assuming stable and predictable conditions, a parasitic contribution may in principle be removed by subtracting a fixed amount of charge from that recorded by the sense amplifier during the reading cycle. In many instances, however, the magnitude and variability of the parasitic contribution makes this inappropriate. Thus, in addition to the manufacturing tolerances for the device, the fatigue and imprint history may vary within wide limits between different cells in the same memory device and even on the same bit line, and the parasitic current may depend strongly upon the device temperature at the time of readout. In addition, the parasitic current associated with a given non-addressed cell on the active bit line may depend on the actual logic state of this cell. In that case the cumulative parasitic current from all non-addressed cells on the active bit line depend on the set of data stored in those cells, which then must define prediction. Thus, there are many drawbacks using a direct reference.
Reference levels can also be obtained from neighbouring cells to deal with the problems indicated above. The neighbouring cells are believed to have the same conditions as the read cells. However, this is not always true, giving rise to problems.
Another implementation is to have a single current integrator providing the signal level corresponding to a known polarization change. A non-unity gain amplifier then distributes this potential as the reference level to a number of sense amplifiers.
All of the above-described methods of obtaining a reference share the problem of non-predictable conditions, whereby there still is a need of another solution for obtaining a true reference.
Hence it is a primary object of the invention to improve referencing of the sensing device, whereby the sensing device becomes resistant to noise and other interfering background signals. Another object of the invention is to provide a sense amplifier, which is not influenced by cumulative signals from non-addressed cells during reading of stored data, obtained i.e. in a so-called xe2x80x9cpartial word readxe2x80x9d. Finally, there is also an object of the invention to provide a read method for use with a sensing device of this kind.
The above-mentioned objects as well as other features and advantages are realized according to the present invention with a sensing device, which is characterized in that the sensing device comprises an integrator circuit for sensing the current response and means for storing and comparing two consecutive read values, one of which is a reference value.
In an advantageous embodiment of the sensing device according to the invention the integrator circuit comprises an operational amplifier and a capacitor connected between an inverting input of the operational amplifier and the output thereof. Preferably the integrator circuit then comprises a switch connected in parallel over the capacitor.
In an advantageous embodiment of the sensing device according to the invention the means for two consecutive reads comprises a first sample/hold circuit for sampling/storing a first read value, a second sample/hold circuit for sampling/storing a second read value, and a comparator circuit connected to the outputs of the sample/hold circuits for determining the state of an addressed memory cell.
Preferably the sample/hold circuits then can comprise capacitors and preferably can the comparator circuit be an operational amplifier.
Finally, a correction circuit can be connected between the second sample/hold circuit and the output of the integrator circuit.
The above-mentioned objects as well as other features and advantages are also realized according to the present invention with a read method which is characterized by two consecutive reads of a memory cell, integrating each read over a predetermined time period respectively to generate a first and a second read value, storing said read values, comparing the stored read values, and determining a logical value dependent on the sensed charge.
In an advantageous embodiment of the read method according to the invention a time delay is introduced between two consecutive reads in a read cycle.